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Electrostatic Discharge (ESD) Testing Techniques

As a leader in ESD testing, EAG Laboratories knows that our customers have a range of needs and that a one size fits all approach does not work. That’s why we have developed a range of IC ESD techniques and Latch-up test offerings to best meet your requirements.

HBM, MM and CDM Testing

Level 1 – Zap only testing (most economical choice) including:

  • Verification of customer provided pin group definition
  • Continuity check on each device
  • Waveform verification
  • Testing according to the standard selected by the customer
  • Detailed report
    • Device ID info
    • Device photos
    • ESD pin groups
    • Waveforms
    • Test summary

Level 2 – Testing with curve trace before and after all zaps (good engineering diagnostic) including:

  • Everything in a Level 1 test
  • Curve trace of all device pins, before ESD stress and after all ESD stresses are complete, on all parts
  • Summary of pins that show curve trace shifts
  • Pictures of curve traces from typical pins that show shifts

Level 3 – Testing with raw waveforms provided (better engineering diagnostic):

  • Everything in a Level 2 test
  • Raw waveform files for all curve traces done on all pins.
  • Data available for download at FTP site (30 days); archived for 5 years at EAG.

 

Level 4 – Testing with curve trace after each zap (detailed engineering diagnostic) including:

  • Everything in a Level 3 test
  • Summary of pins that showed curve trace shifts, along with a description of the test configuration where failure first occurred
  • Data available for download at FTP site (30 days); archived for 5 years at EAG.

Customer defined experiment – Full custom HBM, MM or CDM experiment, including:

  • Priority testing in job queue
  • Engineering support throughout the duration of the test
  • Ability to make engineering changes during the course of the test
  • Customer defined data and reporting
  • Quoted on a per job basis, based on a statement of work and an hourly fee for extra engineering work.

Applicable HBM Specs

  • JESD22-A114 and JS-001-2014 (JEDEC)
  • MIL-STD-883, Method 3015.7 (Department of Defense)
  • AEC-Q100-002 and AEC-Q101-001 (Automotive Electronics Council)
  • ESD STM 5.1-1998 (ESD Association)

Applicable MM Specs

  • JESD22-A115 (JEDEC)
  • AEC-Q100-003 and AEC-Q101-002 (Automotive Electronics Council)
  • ESD STM 5.2-1999 (ESD Association)

Applicable CDM specs

  • JESD22-C101 and JS-002-2014 (JEDEC)
  • AEC-Q100-011 and AEC-Q101-004 (Automotive Electronics Council)
  • ESDA STM 5.3.1-1999 (ESD Association)
Latch Up Testing

Although latch-up testing is performed on the same automated testers as ESD testing, the tests are dramatically different. ESD testing is an un-powered test, whereby pins receive voltage pulses with well-defined combinations of grounded pins on the device under test (DUT). Latch-up testing is performed with the DUT powered, and signals applied to the part to place it in a stable, low current configuration. A specialized ESD/LU worksheet is used to set up automated testers, such as the Thermo Scientific Mk2 or Mk4. Each tester channel has the unique ability to be programmed as a power supply, signal pin, or vectored pin.

The goal in IC latch-up testing is to trigger and monitor a potential latch-up event, where the stress pulse activates a parasitic “Silicon Controlled Rectifier” (SCR) structure within a CMOS or Bi-CMOS process technology. Latch-up testing is fundamentally about the chip physical layout, how circuit blocks are situated relative to one another, and how unanticipated charge is removed from physical elements in the semiconductor material.

Latch-up testing is done according to the last revisions of the JEDEC latch-up specification, JESD78B, JESD78C, JESD78D, or JESD78E. Testing can be done at a customer specified ambient temperature, from 25°C to 150°C. Because there are so many variables, latch-up testing is quoted on a case by case basis, based on the statement of work, estimated engineering time to create a working test, machine time to execute the test, and customer requested reporting.

Applicable LU Specs

  • JESD78 (JEDEC)
  • AEC-Q100-004 (Automotive Electronics Council)
Transmission Line Pulse (TLP) Testing

Transmission Line Pulse testing, or TLP testing, is a method for semiconductor characterization of Electrostatic Discharge (ESD) protection structures. In the Transmission Line Pulse test, high current pulses are applied to the pin under test (PUT) at successively higher levels through a coaxial cable of specified length. The applied pulses are of a current amplitude and duration representative of the Human Body Model (HBM) ESD/LU worksheet request event (or a Charged Device Model – CDM – event in the case of Very Fast TLP, or VF-TLP). The incident and reflected pulses are evaluated, and a voltage-current (V-I) curve is developed that describes the response of an ESD protection structure to the applied TLP stresses. The Transmission Line Pulse test is unique because the current pulses can be on the order of Amps, and the TLP test results can show the turn-on, snap-back, and hold characteristics of the ESD protection structure.

Transmission Line Pulse testing is useful in two very important ways. First of all, TLP may be used to characterize Input/Output (I/O) pad cells on test chips for new process technologies and Intellectual Property (IP). TLP is very useful in developing simulation parameters, and for making qualitative comparisons of the relative merit of different ESD protection schemes for innovative pad cell designs. Secondly, TLP may be used as an electrical failure analysis tool, often in combination with conventional, standards-based component ESD testing.

TLP testing is done according to the ESDA TLP test method, ESDA SP5.5-2003. TLP is quoted on a case by case basis, based on the scope of the work requested; estimated engineering time to perform the test, and customer requested reporting.

Applicable TLP Specs

  • ESDA SP5.5-2003 (ESD Association)