Chip Scale Packages (CSPs) have been around since the early 1990’s. In CSP design, the chip is almost the same size as the substrate. This saves room, but can increase the difficulty of failure analysis including the Dye & Pry process.
The ability to examine solder attachment of a device to a PCB is a very helpful way to quickly evaluate the attach process.
This process is common for other types of mold compound devices, but CSPs tend to be much more brittle and delicate. We have found that the common method of Dye & Pry can result in the cracking and shattering of the die.
The standard process involves cleaning the device that is described in the Dell papers; Dell EMC Dye and Pry Procedure REL0164 Rev A05, IPC-TM-650 2.4.53 Dye and Pull Test Method, & IPC-7095C Design and Assembly Process Implementations for BGAs.
Dye & Pry includes a microscopic examination of board where items such as serial number, identification, lot number, or date codes are captured. We inspect using the provided Accept/Reject Criteria in Appendix A-4 (pg7, Dell EMC REL0164 Rev. A05) and an x-ray is used to examine for any anomalies.
The sample is then cleaned to remove any flux residue from around the solder joints. After cleaning, the device is dyed and then pried to break the solder attachment. Both sides are examined by optical microscopy to observe all the solder attach points. A rating system from the Dell paper is applied to characterize the quality of the solder attachment.
However, this standard method can result in the die breaking in multiple locations with some pieces of the die remaining on the substrate side and some lifting off.
EAG has altered the common Dye & Pry method, which has resulted in a significantly improved rate of success compared with the standard method.
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