Latch Up Testing
Although latch-up testing is performed on the same automated testers as ESD testing, the tests are dramatically different. ESD testing is not done under bias. Latch-up testing is performed with the DUT powered, and signals are applied to the part to place it in a stable, low current configuration. A specialized ESD/LU worksheet is used to set up automated testers, such as the Thermo Scientific Mk2 or Mk4. Each tester channel has the unique ability to be programmed as a power supply, signal pin, or vectored pin.
The goal in IC latch-up testing is to trigger and monitor a potential latch-up event, where the stress pulse activates a parasitic transistor structure within a CMOS or Bi-CMOS process technology. Latch-up testing is fundamentally about the chip’s physical layout, how circuit blocks are situated relative to one another, and how unanticipated charge is removed from physical elements in the semiconductor material.
Latch-up testing is done according to the current revision of the JEDEC latch-up specification, but testing can also be done according to the previous revisions of JESD78. Testing can be done at a customer specified ambient temperature, from 25°C to 125°C. Because there are so many variables, latch-up testing is quoted on a case by case basis, based on the statement of work, estimated engineering time to create a working test, machine time to execute the test, and customer requested reporting.
Applicable LU Specs
- JEDEC: JESD78E
- Automotive Electronics Council: AEC-Q100-004 (based on JESD78E)
Transmission Line Pulse (TLP) Testing
Transmission Line Pulse testing, or TLP testing, is a method for semiconductor characterization of Electrostatic Discharge (ESD) protection structures. In the Transmission Line Pulse test, high current pulses are applied to the pin under test (PUT) at successively higher levels through a coaxial cable of specified length. The applied pulses are of a current amplitude and duration representative of the Human Body Model (HBM) ESD/LU worksheet request event (or a Charged Device Model – CDM – event in the case of Very Fast TLP, or VF-TLP). The incident and reflected pulses are evaluated, and a voltage-current (V-I) curve is developed that describes the response of an ESD protection structure to the applied TLP stresses. The Transmission Line Pulse test is unique because the current pulses can be on the order of Amps, and the TLP test results can show the turn-on, snap-back, and hold characteristics of the ESD protection structure.
Transmission Line Pulse testing is useful in two very important ways. First of all, TLP may be used to characterize Input/Output (I/O) pad cells on test chips for new process technologies and Intellectual Property (IP). TLP is very useful in developing simulation parameters, and for making qualitative comparisons of the relative merit of different ESD protection schemes for innovative pad cell designs. Secondly, TLP may be used as an electrical failure analysis tool, often in combination with conventional, standards-based component ESD testing.
TLP testing is done according to the ESDA TLP test method, ESDA SP5.5-2003. TLP is quoted on a case by case basis, based on the scope of the work requested; estimated engineering time to perform the test, and customer requested reporting.
Applicable TLP Specs
- ESDA SP5.5-2003 (ESD Association)