Latch-up Testing Webinar

In this webinar we introduce latch-up testing which is relevant for CMOS devices with high static power dissipation. 

The recent scaling down of threshold voltage in complementary metal–oxide–semiconductor (CMOS) submicron technologies has resulted in a significant increase in subthreshold leakage current, making the static power dissipation very high. This higher current has also been driven by the need to create complete integrated systems for large data center applications and AI needs. There are some unique challenges in performing the latch-up test on these devices, and EAG has developed a number of solutions to manage them.

This webinar is for anyone interested in latch-up test, and it is particularly relevant for companies who are designing CMOS devices with high static power dissipation.

In this webinar we will cover:

  • A description of the latch-up phenomenon
  • An overview of the JESD78E latch-up test
  • The test constraints associated with commercially available latch-up testers
  • The challenges associated with performing latch-up on high current devices
  • An overview of EAG’s approach to the high current challenges

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